逻辑操作与容错协议logical
分段式容错逻辑门
把会传播错误的非横向逻辑线路分成若干片段，并在片段之间插入纠错，使任一允许 fault set 的传播在检查点仍可纠正。
- 成熟度
- research
- 重要度
- 重要主题
- 证据
- 1 篇代表来源
01
范围与辨析
必须公开 circuit pieces、intermediate EC、contagious error 集与终态容错证明；普通门分层或为了调度而切片不构成 pieceable fault tolerance。
02
核心机制与研究判断
核心机制
- nontransversal circuit pieces
- intermediate error correction
- contagious error control
- small-code universal gates
适用与评测约束
- Code Family
- must be declared
- Fault Model
- fault set and propagation must be declared
- Logical Gate Set
- must be declared
- Overhead Metrics
- space time and acceptance must be declared
- Ancilla Resources
- must be declared
- Measurement Feedback
- must be declared
03
全栈位置与直接关系
logical/protocol/pieceable04