实验与里程碑experiment
中性原子逻辑处理器实验
在可重构中性原子阵列上编码多个逻辑量子比特并执行逻辑门、feed-forward 或程序化逻辑线路。
- 成熟度
- 实验阶段
- 重要度
- 重要主题
- 证据
- 1 篇代表来源
01
范围与辨析
记录编码、物理/逻辑量子比特数、筛选或纠错方式、逻辑门集和算法指标；error detection/postselection 必须与持续纠错明确区分。
02
核心机制与研究判断
核心机制
- logical-qubit count
- zoned architecture
- transversal gates
- mid-circuit feed-forward
- algorithmic logical circuits
适用与评测约束
- Code
- must be declared
- Decoder
- must be declared
- Qec Rounds
- must be declared
- Noise Level
- must be declared
- Code Distance
- must be declared or not applicable
- Physical Scale
- must be declared
- Primary Metric
- must be declared
- Hardware Platform
- must be declared
03
全栈位置与直接关系
experiment/platform/neutral-atom-logical04